Système de Gestion Technique Décentralisé 68000 CPU Board

VCFed forum member jplr asked about this board he had, and then kindly gave it to me.

It's not VME.

OK, so what have we here?

• 8 MHz 68000
• 6 x 27512 EPROMs - 384 kilobytes
• 2 x CXK58256 32k x 8 RAM - 64 kilobytes
• 6 x TC5565APL 8k x 8 RAM - 48 kilobytes
• Two TIL311 hex display chips, presumably for diagnostics
• MC146818 RTC
• MK68564N Dual UART
• MK68901N Multi-function Peripheral - I/O, timers and a UART
• A whole bunch of 74LS245 buffers connecting the 68000 to the bus on P2 (which is why I'm saying this is not VME.
• Space for four chips, not fitted, connecting to P1 for I/O. I suspect these are MC68681s.
• What looks like serial on J3, but with a 1489 RS-232 receiver and a 26LS30 RS-422 driver. This is a little bit weird.

MN2.8 (M868901 SO) -> MN16.13 (LS14) -> MN16.12 -> MN11.2 (26LS30 InA) -> MN11.15 (OutA) -> DB25F.3
DB25F.2 -> MN15.1 (MC1489 in A) -> MN15.3 (out A) -> MN2.9 (M868901 SI)

<googlefodder>Front panel has ND1311, PCB has NDTU-1311</googlefodder>

ROM

I dumped the ROM (of course) and found some interesting strings.

VRTX/68000 Rev. 3.20  Copyright 1986, Hunter & Ready, Inc.  

VRTX/68000 was a commercial OS, there is documentation on BitSavers. It's not NuVRTX, strings will give you that but the Nu is actually an RTS.

X25 V1.9l 31/08/89

Presumably they bought the X.25 stack from someone as well. Who knows.

                             SILICON SOFTWARE
(c) 1989, 90, 91, 92, 93, 94 Microtec Research, Inc. All rights reserved
Unpublished-rights reserved under the copyright laws of the United States
                          RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to restrictions
as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data &
Computer Software clause at DFARS 252.227-7013
MICROTEC RESEARCH, INC., 2350 MISSION COLLEGE BLVD., SANTA CLARA, CA 95054

On the bottom of all six EPROMs.

ESD

This logo appears in a couple of places and the EPROM labels read END4081007A01 ESD.

6023-081 is also significant, this number is on the three PALs as well as on a jumper block and two PCBs, function at this stage unknown.

The bus

Memory Map

I buzzed out the connections to the PAL, wrote some code for my trusty Expro 80 to toggle the PAL pins, and found the following.

MN49, 6023-081-027, a PAL16L8:

A23   1   20  Vcc
A22   2   19  ->
A21   3   18  ->
A20   4   17  -> MN26 pin 1 (IOSEL) 
A19   5   16  ->
A18   6   15  ->
A17   7   14  R/~W
A16   8   13  /AS
A15   9   12  -> LS138 E2
GND   10  11  A14

Pin 12: 0x000000-0x03FFFF Read Only
        0x0D4000-0x0FFFFF R/W
Pin 15: 0x0D4000-0x2DFFFF R/W
Pin 16: 0x000000-0x03FFFF Read Only
Pin 17: 0x070000-0x073FFF R/W (I/O area)
Pin 18: 0x870000-0x87FFFF R/W
Pin 19: 0x870000-0x87FFFF R/W (same as pin 18)

Pin 12 enables MN55, the 74LS138 that does the memory decoding.

Pin 17 enables MN26, a PAL20L10. MN26 in turn selects the various I/O devices.

MN53, 6023-081-028, a PAL16L8. Three of the outputs go to MN64, a 74LS138, the outputs of which drives the chip selects for the EPROMs, RAMs, and expansion memory board.

A23   1   20  Vcc
A22   2   19  -> LS138 A0
A21   3   18  -> LS138 A1
A20   4   17  -> LS138 A2
A19   5   16  N/C
A18   6   15  N/C
A17   7   14  R/~W
A16   8   13  /AS
A15   9   12  ->
GND   10  11  A14

This is what the PAL gives me. Note that MN49 pin 12 also has to be low, so only the 0x000000-0x03FFFF and 0x0D4000-0x0FFFFF areas actually select anything.

Also

Pin 12: 0x000000-0x03FFFF Read Only
        0x0D4000-0x1FFFFF R/W
Pin 15: Always 1
Pin 16: Always 1

While MN49 uses /AS (i.e. outputs are only low when /AS is low), as far as I can see MN53 ignores /AS.

When I concatenate the three ROMs (i.e. the image I linked earlier) and disassemble it, all makes sense. The initial stack pointer is 0x0F0100 which is in RAM0, and the RESET vector points to 0x05A9FC which is in ROM2 and the code there looks appropriate. However. With the above map, ROM2 is not in the contiguous address space.

I am of the opinion that the ROM/RAM configuration does not match the PALs fitted, that this was some kind of a lab board and not in a working configuration.

So I suspect I should give up on making this thing work as-is (what would I do with it anyway?) and make it into a useable SBC. For this I need:

• Information on how the jumpers select which devices can be used in which EPROM / RAM socket
• New PALs to change the memory map to something that works for me

The jumpers

27C512 64k x 8
27C256
27C128

58256 32k x 8 62256 27 /WE 1 A14
5565 8kx8 6264

The PALs

For starters, I re-created the equations to generate JED files to program two GALs which are functionally identical to 6023-081-027 and 6023-081-028.

--- Work in Progress --- Nothing to see here --- let me know if you also have one of these ---

<ECP>

MN49

Pin 12: 0x000000-0x04FFFF Read Only
        0x0D4000-0x1FFFFF R/W
Pin 15: 0x0D4000-0x2DFFFF R/W
Pin 16: 0x000000-0x04FFFF Read Only
Pin 17: 0x070000-0x073FFF R/W
Pin 18: 0x870000-0x87FFFF R/W
Pin 19: 0x870000-0x87FFFF R/W (same as pin 18)

MN53

Pin 12: 0x000000-0x04FFFF Read Only
        0x0D4000-0x1FFFFF R/W
Pin 15: Always 1
Pin 16: Always 1

</ECP>